PCB Tools
PCB Impedance Calculator Microstrip, Stripline & CPW
Solve characteristic impedance (Z0) from your trace geometry in real time. Enter Dk, trace width, copper weight and dielectric height — get an instant IPC-2141 estimate and a 50 / 90 / 100Ω target check to size your stackup before you order.
Outer-layer trace over one reference plane (exposed to air on top).
1 oz ≈ 1.37 mil (1.37 mil)
Characteristic impedance
Common target check (±10%)
Nearest target: 50Ω(2.1% off — within ±10%).
Formula (IPC-2141 / Wadell)
Z0 = (87 / √(Er+1.41)) · ln( 5.98·h / (0.8·w + t) )First-order estimate for stackup planning. Etch, resin content, copper roughness and solder-mask shift the real value — AtlasPCB verifies every controlled-impedance board by TDR.
Have your target impedance? Skip the guesswork — our engineers design the stackup and verify it by TDR.
Get Instant QuoteHow Controlled Impedance Works
The characteristic impedance a trace presents to a fast signal is set by geometry, not the copper alone. Four variables dominate: the substrate dielectric constant (Er / Dk), the trace width, the copper thickness, and the dielectric height to the reference plane. Widen the trace or shrink the dielectric and Z0 drops; raise the dielectric height or Dk and it rises. The closed-form equations used by this calculator come from IPC-2141A (Design Guide for High-Speed Controlled Impedance Circuit Boards) and the Wadell transmission-line models — the same first-order math fabs use before a field solver refines the final stackup.
Microstrip
An outer-layer trace over a single reference plane, exposed to air on top. Simplest and cheapest controlled-impedance geometry; tuned almost entirely by trace width and dielectric height. Common for 50Ω single-ended routing.
Z0 = (87/√(Er+1.41))·ln(5.98·h/(0.8·w+t))Stripline
An inner-layer trace centered between two reference planes, fully embedded in dielectric. Tighter field confinement and better noise immunity than microstrip — ideal for dense differential pairs like DDR and PCIe — at the cost of a symmetric stackup.
Z0 = (60/√Er)·ln(4·b/(0.67·π·(0.8·w+t)))Coplanar Waveguide (CPW)
A trace flanked by coplanar ground pours, usually with a plane below (grounded CPW / GCPW). The gap to the side grounds is a primary tuning variable, giving low-loss, well-behaved impedance for RF and mmWave.
Z0 = (60π/√Eeff)/(K(k1)/K(k1′)+K(k2)/K(k2′))GCPW note: the calculator uses the conformal-mapping (elliptic-integral) approximation for conductor-backed coplanar waveguide, with k1 = w/(w+2s) for the coplanar grounds, k2 = tanh(πw/4h)/tanh(π(w+2s)/4h) for the lower plane, and εeff from the ratio of complete elliptic integrals K(k)/K(k′). Copper thickness is treated as zero in the GCPW model (its effect is second-order for typical geometries).
Why ±10% Tolerance Matters — and How TDR Proves It
A calculated impedance is a target, not a guarantee. Every point where the real trace deviates from that target is an impedance discontinuity, and each discontinuity reflects part of the signal back toward the source. Those reflections erode eye height and timing margin on high-speed links — the faster the edge rate, the less mismatch a channel tolerates.
High-speed interfaces (USB, PCIe, DDR, HDMI, Ethernet) are specified around a nominal impedance, so most controlled-impedance fabs target ±10%. Etch profile (trapezoidal traces), resin content, copper roughness, solder-mask coverage and glass-weave skew all push the finished board off the ideal number — which is exactly why a calculator estimate must be verified.
TDR (Time Domain Reflectometry) launches a fast edge into a test coupon built from your board's real trace geometry and reads the reflected waveform to map the actual impedance profile along the line. AtlasPCB places coupons on every controlled-impedance panel, TDR-tests 100% of those boards (no statistical sampling), and ships the measured report — holding ±8% single-ended and differential, and ±10% for GCPW.
Reflections cost margin
Every mismatch reflects energy; the sum eats into your eye height and timing budget.
Process shifts the number
Etch, resin, copper roughness and solder mask move the real Z0 away from the calculated value.
100% TDR tested
Coupons on every panel, measured against target — not simulated and hoped.
±8% held, report included
Boards outside the window do not ship. Measured TDR report with every order.
Reference: Common 50Ω / 90Ω / 100Ω Geometries
Ballpark starting points on FR-4 (Dk ≈ 4.3) with 1 oz copper, rounded for planning. Differential pairs also depend on edge coupling (trace-to-trace gap), so treat the diff rows as approximate. Plug your real Dk and stackup into the calculator above, then let our engineers finalize the geometry.
| Target Z0 | Type | Geometry | Material | Trace / gap | Dielectric |
|---|---|---|---|---|---|
| 50Ω | Single-ended | Microstrip | FR-4 (Dk 4.3) | 13 mil | h = 8 mil to plane |
| 50Ω | Single-ended | Stripline | FR-4 (Dk 4.3) | 6 mil | b = 20 mil (plane sep.) |
| 50Ω | Single-ended | GCPW | Rogers RO4350B (Dk 3.48) | 20 mil | s = 10 mil, h = 10 mil |
| 90Ω | Differential | Microstrip | FR-4 (Dk 4.3) | 5 mil / 5 mil gap | h ≈ 4 mil to plane |
| 100Ω | Differential | Microstrip | FR-4 (Dk 4.3) | 5 mil / 8 mil gap | h ≈ 4 mil to plane |
| 100Ω | Differential | Stripline | FR-4 (Dk 4.3) | 4 mil / 10 mil gap | b ≈ 20 mil (plane sep.) |
Single-ended rows are computed with the IPC-2141 microstrip / stripline equations this page uses; GCPW and differential rows are representative. Exact widths depend on the finished dielectric height, copper weight and laminate Dk of your specific stackup.
Ready to hit these targets in copper?
Upload your design and we'll design the impedance stackup, then TDR-verify every board.
FAQ
PCB Impedance Calculator FAQs
How accurate is this PCB impedance calculator?
It uses the IPC-2141 / Wadell closed-form approximations, typically within a few percent of a 2D field solver for common single-ended geometries. Great for first-pass stackup planning — but etch, resin content, copper roughness, solder mask and glass weave shift the real value, so AtlasPCB models your exact stackup and TDR-verifies every controlled-impedance board.
Microstrip vs stripline vs coplanar waveguide — which do I use?
Microstrip (outer layer, one plane, air on top) is simplest and cheapest for 50Ω single-ended. Stripline (inner layer, between two planes) gives tighter confinement and noise immunity for dense DDR/PCIe pairs. Coplanar waveguide (grounded CPW) adds side-ground pours whose gap tunes impedance, ideal for RF and mmWave.
What inputs does the calculator need?
Dielectric constant (Er / Dk), trace width, copper thickness (in oz, converted at 1 oz ≈ 1.37 mil) and dielectric height to the plane. Stripline adds plane-to-plane separation (b); coplanar waveguide adds the gap to the side ground (s). All lengths are in mils.
Why does impedance need to stay within ±10%?
Impedance discontinuities cause reflections that degrade signal integrity — reflected energy at every mismatch erodes eye height and timing margin. High-speed specs (USB, PCIe, DDR, Ethernet) assume a nominal impedance, so most fabs target ±10%. AtlasPCB holds ±8% single-ended and differential, ±10% for GCPW.
How do you verify impedance in production (TDR)?
TDR (Time Domain Reflectometry) sends a fast edge into a test coupon built with your board’s trace geometry and measures the reflected waveform to read the actual impedance along the line. We place coupons on every controlled-impedance panel, test 100% of those boards, and include the measured report with your order.
From calculated target to verified board
Send us your impedance targets and stackup. We design the geometry, build it, and ship a TDR measurement report with every order.