Glass Core Substrate
CTE 3.2 ppm/C matched to silicon | Ultra-flat to 1um warpage | Enabling AI chiplet interposers and HBM integration at unprecedented scale.
3.2
ppm/C CTE
<1um
Warpage
AI
Chiplets
HBM
Integration
What is Glass Core Substrate?
Glass core substrates represent the most significant advancement in IC packaging technology this decade. By replacing organic (BT/ABF) or silicon interposer cores with precision glass, the substrate achieves CTE (3.2 ppm/C) matched nearly perfectly to silicon (2.6 ppm/C) — enabling larger interposers, tighter bump pitches, and more chiplet integration than any organic substrate can support.
The driving force is AI chip packaging. NVIDIA, AMD, and Intel all face the reticle limit — individual dies cannot exceed approximately 800mm2. To build larger AI accelerators, multiple chiplets must be connected through an interposer. Silicon interposers work but are prohibitively expensive at scale. Glass core provides equivalent CTE matching at a fraction of the cost.
Intel's announcement of glass core substrate technology in 2023 signaled the industry transition. By 2026, multiple OSAT (Outsourced Semiconductor Assembly and Test) providers offer glass core interposer fabrication for AI accelerator packages that integrate 4-8 compute chiplets with 4-12 HBM stacks on a single 100mm+ interposer.
Silicon-Matched CTE
3.2 ppm/C eliminates thermal warpage at chiplet-to-interposer interfaces.
Ultra-Flat Surface
Sub-micron warpage enables direct bonding and fine-pitch flip-chip.
AI Chiplet Scale
Interposers exceeding 100mm — impossible with organic substrates.
Cost vs Silicon
Fraction of silicon interposer cost at equivalent CTE matching.
Glass Core Substrate Key Properties
Representative values from the manufacturer datasheet.
| Property | Value | Why it matters |
|---|---|---|
| CTE | 3.2 ppm/C | Near-perfect match to silicon (2.6 ppm) and SiC (4.0 ppm). |
| Surface flatness | <1 um warpage | Enables hybrid bonding and fine-pitch assembly. |
| Dielectric constant | ~4.6 @ 1 GHz (glass) | Standard glass — specialty low-Dk glass available. |
| Thickness range | 100-400 um core | Ultra-thin cores for package height reduction. |
| Via technology | TGV (Through-Glass Via) | Laser or photo-formed vias through glass core. |
| Maximum interposer size | 100+ mm | Exceeds silicon reticle limit for multi-chiplet. |
| Thermal conductivity | 1.0-1.4 W/mK | Higher than organic, lower than silicon. |
| Line/space capability | 2-5 um (with ABF RDL) | Advanced RDL on glass core surface. |
| Operating temperature | -55C to +200C | Wide range for AI compute thermal management. |
Glass Core: The AI Packaging Revolution
Current AI accelerators (NVIDIA B200, AMD MI350) use silicon interposers to connect HBM stacks to compute dies. Silicon interposers at 65mm x 65mm cost $200-400 each and are capacity-constrained at TSMC. Glass core interposers at the same size cost an estimated 30-50% less and can be manufactured at multiple suppliers without leading-edge semiconductor equipment.
The CTE matching advantage becomes critical at scale. A 100mm organic (BT) interposer with CTE mismatch of 8-10 ppm versus silicon would warp 50-100um during thermal cycling — making fine-pitch bump connections impossible. Glass at 3.2 ppm versus silicon at 2.6 ppm warps less than 5um — enabling sub-50um bump pitch across the entire interposer.
Through-Glass Via (TGV) technology has matured to support the wiring density required for chiplet interconnect. Laser-formed TGVs at 50um diameter on 100um pitch provide sufficient I/O density for die-to-die communication, while photo-formed TGVs enable even finer pitches approaching silicon TSV density at dramatically lower cost.
AI Accelerator Packaging
Enabling next-generation multi-chiplet AI packages beyond reticle limits.
HBM Integration
Connecting 4-12 HBM stacks to compute chiplets on single interposer.
30-50% Cost Reduction
Versus silicon interposers at equivalent CTE and scale.
Sub-50um Bump Pitch
Ultra-flat surface enables finest interconnect pitches.
Interposer Technology Comparison
Glass core versus alternative interposer technologies for AI packaging.
| Material | Dk | Df | Best For |
|---|---|---|---|
| Glass Core InterposerThis page | 3.2 ppm CTE | Moderate | Best value — AI chiplets, HBM, CTE-matched at scale. |
| Silicon Interposer (TSV) | 2.6 ppm CTE | Highest | Finest pitch — current NVIDIA/AMD standard, capacity limited. |
| Organic (ABF) Interposer | 12-15 ppm CTE | Lowest | Cost effective — limited to larger bump pitches, smaller dies. |
| Fan-Out (FOWLP) | Variable | Moderate | No core — limited I/O, suited for mobile/IoT packages. |
| Silicon Bridge (EMIB) | 2.6 ppm CTE | Moderate | Intel approach — localized silicon bridges in organic substrate. |
Glass Core Substrate Applications
AI accelerator interposers, HBM memory integration, chiplet-to-chiplet interconnect, next-gen advanced packaging
AI Accelerators
Next-gen GPU and custom AI ASIC multi-chiplet packages.
HBM Interposers
High-bandwidth memory integration with compute chiplets.
Chiplet Architectures
Heterogeneous die integration (compute + I/O + memory controllers).
Networking ASICs
800G+ switch ASIC packages exceeding single-die reticle limits.
Power Delivery
Ultra-low-impedance power distribution for high-current AI dies.
Photonics Integration
Co-packaged optics with electronic chiplets for AI interconnect.
Glass Core Substrate Design Considerations
Glass core design requires TGV (Through-Glass Via) placement planning early in the architecture phase. TGV pitch, diameter, and placement constraints differ from organic vias or silicon TSVs. Work with the substrate vendor to understand their specific TGV capability before committing floorplan.
Thermal management on glass core is less favorable than silicon (1.0-1.4 W/mK versus 150 W/mK for silicon). AI accelerator packages require dedicated thermal solutions — heat spreader lids, high-performance TIM, and active cooling — that do not rely on lateral heat spreading through the interposer.
Get Instant QuoteTGV Planning
Understand vendor TGV pitch and diameter constraints before floorplan.
Thermal Design
Glass does not spread heat — dedicated thermal solutions required.
Warpage Budget
Near-zero warpage enables aggressive bump pitch — exploit this advantage.
RDL Design
Fine-line RDL (2-5um) typically built with ABF on glass core surface.
Genuine Glass Core Substrate, Verified on Every Order
Material CoC
Certificate of Conformance with lot number ships with every order.
Stock Verified
We confirm laminate availability before order confirmation.
No Substitutions
Specified material guaranteed — never swapped without written approval.
FAQ
Glass Core Substrate Questions
What is glass core substrate?
A package substrate using precision glass as the core material, providing CTE 3.2 ppm/C matched to silicon for large-area AI chiplet interposers with minimal warpage.
Glass core vs silicon interposer?
Glass provides similar CTE matching at 30-50% lower cost without requiring leading-edge semiconductor fab capacity. Silicon offers finer TSV pitch and better thermal conductivity.
What AI chips use glass core?
Multiple AI accelerator companies are transitioning from silicon to glass core interposers for next-generation packages. Intel publicly announced glass core technology in 2023.
What are TGVs?
Through-Glass Vias — vertical electrical connections through the glass core, analogous to TSVs in silicon. Formed by laser or photo-lithographic processes.
Can AtlasPCB produce glass core substrates?
We offer glass core substrate fabrication through advanced packaging partnerships. Contact our engineering team for capability assessment on your specific design requirements.
Exploring glass core for AI packaging?
Glass core interposers — CTE-matched to silicon, enabling multi-chiplet AI at scale. Contact our advanced packaging team.
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