High Speed PCB Manufacturing
High-Speed PCB Manufacturer Signal Integrity to 112G PAM4
PCB fabrication engineered for 56G and 112G SerDes channels. Ultra-low-loss materials, precision impedance control, optimized via structures, and verified insertion loss on every production lot.
Capabilities
High Speed PCB Capabilities
Everything your 56G/112G channel needs from the board.
Ultra-Low-Loss Materials
Megtron 6/7, Astra MT77, IT-968SE, S7439, TU-872 SLK. Hybrid stackups with FR-4 on non-critical layers to reduce cost.
Back-Drilling
CNC-controlled stub removal on through-hole vias. Depth accuracy ±0.1mm. Cross-section verified on first article.
Impedance Control
Single-ended and differential ±8% tolerance standard. Enhanced ±5% available. TDR tested 100%.
Low-Roughness Copper
HVLP and HVLP2 foils (Rz under 2-3um) for inner and outer layers. Reduces conductor loss 15-25% vs standard ED copper.
High Layer Count
Up to 40 layers with sequential lamination. Tight registration for pad-on-via alignment across 20+ layer transitions.
Insertion Loss Testing
VNA-based insertion loss measurement on test coupons. Verifies that production boards meet your loss budget per inch.
Anti-Pad Optimization
Non-functional pad removal (NPTH) and optimized anti-pad geometry to minimize via-to-trace coupling and return loss.
Glass Weave Mitigation
Spread-glass prepreg and trace rotation options to reduce fiber-weave skew on differential pairs above 25 Gbps.
Mixed Dielectric Stackup
Combine ultra-low-loss laminates on signal layers with standard FR-4 on power/ground. Saves 30-50% vs all-low-loss.
Signal Integrity
Why High Speed PCB Is Different
At 28 Gbps NRZ and above, the PCB is no longer just a mechanical carrier for components. It becomes the dominant contributor to channel loss. A standard FR-4 board running at 56 Gbps PAM4 will lose 1.0-1.5 dB/inch on inner-layer striplines, which exhausts most transceiver equalization budgets before the signal reaches the receiver. High speed PCB manufacturing treats the board as a transmission line system from the first day of stackup planning through final electrical verification.
The challenge is threefold. First, dielectric loss in the substrate material dominates above 10 GHz, so the laminate selection determines whether your channel will close. Second, copper roughness on the trace surface adds 0.2-0.5 dB/inch at 28 GHz depending on foil type, and this roughness is invisible in your EDA tool. Third, via stubs, even 5-mil stubs left by incomplete back-drilling, create resonances that destroy signal integrity at specific frequencies. Managing all three variables simultaneously, in production at volume, is what separates a high speed PCB manufacturer from a standard one.
Dielectric Loss Control
We stock Megtron 6 (Df 0.002), Megtron 7 (Df 0.001), Isola Astra MT77 (Df 0.0017), ITEQ IT-968SE (Df 0.0015), and Shengyi S7439 (Df 0.0013). Material selection is matched to your data rate and channel length. At 112G PAM4, the difference between Df 0.002 and 0.001 is whether your channel closes or fails.
Copper Roughness Management
Standard electrodeposited copper (ED foil) has Rz roughness of 5-8um. At 28 GHz, that adds 0.3-0.5 dB/inch to your loss budget. We offer HVLP (Rz under 3um) and HVLP2 (Rz under 2um) foils as standard options for high speed stackups. The roughness is specified on your stackup drawing and verified by cross-section.
Via Stub Elimination
Via stubs above 10 mil create quarter-wave resonances below 20 GHz that appear as deep notches in your S21 plot. We back-drill every high speed via to within 0.1mm of the target layer, verified by cross-section on first article. For designs above 56G, we recommend blind/buried via structures that eliminate stubs entirely.
Insertion Loss Verification
VNA-based insertion loss measurement on test coupons matched to your actual trace geometry verifies that production boards meet your loss budget per inch — catching material lot-to-lot variation before it reaches your assembly line.
High-Speed Boards We Build
Controlled-impedance multilayers, in the wild
Manufacturing Process
From Stackup Review to Verified Loss
Every high speed PCB order begins with a stackup review and ends with electrical verification. Here is what happens on our floor — and why each control matters for your loss budget.
Stackup & Channel Review
Every order begins with a stackup review — we model your target impedance and estimate insertion loss per inch from your chosen material and copper roughness, confirming fabrication can deliver what your channel simulation predicts.
Material Selection
The laminate is matched to your data rate and channel length — Megtron 6/7, Astra MT77, IT-968SE, or S7439. At 112G PAM4 the choice between Df 0.002 and Df 0.001 decides whether the channel closes.
Impedance-Controlled Fabrication
Single-ended and differential lines built to ±8% standard (±5% enhanced) and TDR tested 100%. Etch factor and dielectric height are held tight so measured impedance matches the stackup model.
Sequential Lamination
Up to 40 layers with sequential lamination, holding registration tight enough for pad-on-via alignment across 20+ layer transitions on low-loss laminate.
Back-Drilling with X-ray Depth Control
Back-drill depth is set by X-ray measurement of inner-layer position on each panel — not a fixed depth from the board surface — compensating for lamination thickness variation and holding stub length below 5 mil at ±0.1mm.
Pre-Production Test Vehicle
For 112G PAM4 designs we run pre-production test vehicles to verify insertion loss before committing your full lot, catching material lot-to-lot variation, etch factor drift, and plating thickness effects before assembly.
Insertion Loss Verification
VNA-based S-parameter measurement on coupons matched to your trace geometry reports insertion loss (S21) and return loss (S11) from DC to your Nyquist frequency, per-lot or per-panel.
Finish & Final Electrical Test
Solder mask, surface finish, and full electrical test complete the board, with first-article cross-sections confirming back-drill depth and impedance on every new design.
Materials & Stackup
Matched to your data rate and channel length
Choosing the right laminate is the single decision that determines whether your channel closes. We stock the full low-loss range — from Megtron 7 (Df 0.001) for 800G switches and AI accelerators down to standard FR-4 for short-reach DDR4 and USB 2.0.
Hybrid stackups place ultra-low-loss material only on the signal layers while keeping standard FR-4 on power and ground, cutting 30-50% off an all-low-loss construction with negligible impact on channel performance.
| Material | Dk | Df | Max Data Rate | Best For |
|---|---|---|---|---|
| Megtron 7 | 3.1 | 0.001 | 112G PAM4 | 800G switches, AI accelerators |
| ITEQ IT-968SE | 3.16 | 0.0015 | 112G PAM4 | AI servers, HPC |
| Isola Astra MT77 | 3.00 | 0.0017 | 112G PAM4 | Data center, 800GbE |
| Shengyi S7439 | 3.0 | 0.0013 | 112G PAM4 | Cost-optimized 112G |
| Megtron 6 | 3.4 | 0.002 | 56G PAM4 | PCIe Gen5, 400GbE |
| Shengyi S7040G | 3.72 | 0.0089 | 28G NRZ | PCIe Gen4, 25GbE |
| Isola 370HR | 4.04 | 0.021 | 10G NRZ | DDR4, USB 3.2, GbE |
| Standard FR-4 | 4.2-4.7 | 0.02 | 5-10G | DDR4 short reach, USB 2.0 |
Not sure which material your channel budget requires? Send us your data rate, channel length, and equalization capability. Our SI engineers will model the channel and recommend the most cost-effective laminate. See our full material library for detailed datasheets.
Design Guidelines
DFM for High-Speed Success
A handful of design choices decide whether your channel closes in production. These are the DFM recommendations our SI engineers apply to every high speed review.
Via Design
For signals above 25 Gbps, avoid through-hole vias routed on inner layers unless back-drilling is specified. Preferred: blind/buried vias or through-hole with back-drill. Anti-pad diameter should be 20 mil larger than drill diameter minimum to control return loss. Remove non-functional pads on all non-connected layers.
Trace Geometry
Target 4-5 mil trace width for 100-ohm differential stripline on Megtron 6 (Dk 3.4, 4 mil dielectric). Below 3.5 mil, etch factor variability starts to dominate impedance tolerance. Where possible, widen traces and increase dielectric height rather than shrink geometry. This reduces both loss and manufacturing risk.
Reference Plane Integrity
Every high speed trace must have an uninterrupted reference plane directly above or below. If the signal transitions layers (via), the return current must also transition via a nearby ground via within 20 mil. Split planes under differential pairs will cause common-mode conversion and EMI.
Material Specification
Specify the laminate system by name, not by generic Dk/Df values. "Dk 3.4, Df 0.002" matches five different products with different mechanical and thermal properties. Call out the exact material (e.g., "Panasonic Megtron 6 R-5775N") and the foil type (HVLP or HVLP2) explicitly in your fab notes.
Applications
High-Speed Systems We Build For
We fabricate boards for these high speed systems daily.
AI / HPC Servers
GPU interconnect backplanes at 112G PAM4, NVLink and PCIe Gen5/6 switch boards, AI training cluster fabric. Typically 20-32 layers on Megtron 7 or IT-968SE with HVLP2 copper.
Data Center Networking
400G and 800G Ethernet switch line cards. Retimer boards, optical module host boards, and orthogonal midplane connectors. Channel loss budgets of 25-30 dB at Nyquist frequency.
5G Infrastructure
Baseband processing cards with 25G CPRI/eCPRI links. Fronthaul and midhaul interface boards. Mixed-material stackups combining low-loss signal layers with standard power distribution.
High-Speed Test Equipment
Oscilloscope front-end boards, BERT interposer cards, and channel emulation boards requiring insertion loss repeatability across production lots to within 0.1 dB/inch.
Automotive Ethernet
In-vehicle 10GBASE-T1 and 25GBASE-T1 domain controllers. Zonal architecture backbone boards requiring low-loss with automotive-grade laminate (Tg 170+, CAF resistant).
Memory Modules
DDR5 RDIMM and LRDIMM substrates, CXL memory expander boards, and HBM interposers. Tight impedance matching (±5%) and length matching within 2 mil for data bus groups.
The Difference
Why High-Speed at AtlasPCB
The hard part of high speed isn't whether the board can be made — it's whether the finished channel matches your simulation. Our process is built around proving it does.
SI Engineering Review
Our SI engineers model your channel, estimate per-inch loss, and recommend material or geometry changes before you commit — free for production orders.
Verified Loss Budget
VNA insertion-loss testing on coupons matched to your trace geometry confirms production boards meet the loss budget your simulation predicted.
Back-Drill Precision
X-ray inner-layer measurement per panel holds stub length below 5 mil at ±0.1mm, killing the resonances that notch your S21 plot.
Low-Loss Material Stock
Megtron 6/7, Astra MT77, IT-968SE, and S7439 in stock, with hybrid stackups to place low-loss laminate only where the channel needs it.
FAQ
High Speed PCB Questions
We fabricate boards running up to 112 Gbps PAM4 per lane (800G Ethernet, PCIe Gen6). The key constraint is material selection and via structure, not our process capability. We will help you select the right combination for your target data rate.
Megtron 6 (Df 0.002) handles 56G PAM4 channels up to about 10 inches. For 112G PAM4 or channels longer than 8 inches at 56G, move to Megtron 7, Astra MT77, or IT-968SE (Df 0.001-0.0017). We can model your specific channel to confirm.
Ultra-low-loss materials (Megtron 6/7 class) typically add 40-80% to board cost versus standard FR-4, depending on layer count and panel size. Hybrid stackups (low-loss on signal layers, FR-4 on power/ground) reduce the premium to 25-45%.
Yes. We offer VNA-based S-parameter measurement on test coupons matched to your actual trace geometry. The report gives you measured insertion loss (S21) and return loss (S11) from DC to your Nyquist frequency. Available per-lot or per-panel.
Our back-drilling uses X-ray measurement of actual inner layer position on each panel, then drills to within ±0.1mm (4 mil) of the target depth. Stub length is typically held below 5 mil. First article cross-sections confirm depth on every new design.
Yes, and we recommend them. Placing ultra-low-loss material only on signal layers while using standard FR-4 on power and ground layers saves 30-50% versus an all-low-loss construction, with negligible impact on channel performance.
Need high-speed PCBs?
Upload your Gerbers for an instant quote, or send your stackup for a free channel review before production.